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91400 rm (im) hk-1/28 ver.2.04 80698 preliminary overview the LC87F5164A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks: - cpu: operable at a minimum bus cycle time of 100ns - 64k bytes flash rom (re-writeable on board) - 1024 byte ram - two high performance 16 bit timer/counters (can be divided into 8 bit units) - two 8 bit timers with prescalers - timer for use as date/time clock - two synchronous serial i/o ports (with automatic block transmit/receive function) - one asynchronous/synchronous serial i/o port - 12-bit pwm 2 - 8-channel 8-bit ad converter - high speed 8-bit parallel interface - 19-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features (1) read only memory (flash rom) - single 5v power supply, writeable on-board. - block erase in 128 byte units - 65536 8 bits (LC87F5164A) (2) bus cycle time - 100ns (10mhz) note: the bus cycle time indicates rom read time. 8-bit single chip microcontroller with 64k-byte feprom and 1024-byte ram on chip LC87F5164A ordering number : enn*5924b cmos ic
LC87F5164A 2/28 (3) minimum instruction cycle time : 300ns (10mhz) (4) ports - input/output ports each bit data direction programmable 59 (p1n,p2n,p3n,p70 to p73,p8n,pan,pbn,pcn,s2pn) nibble data direction programmable 8 (p0n) - input ports 2 (xt1,xt2) - pwm output ports 2 (pwm0,pwm1) - oscillator pins 2 (cf1,cf2) - reset pin 1 ( res ) - power supply 6 (vss1 to 3,vdd1 to 3) (5) timers - timer0: 16 bit timer/counter with capture register mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register - timer1: pwm/16 bit timer/counter (with toggle output) mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer/counter (with toggle output) mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as pwm output. - timer4: 8-bit timer with 6-bit prescaler - timer5: 8-bit timer with 6-bit prescaler - base timer 1. the clock signal can be selected from any of the following: sub-clock (32.768khz crystal oscillator), system clock, and prescaler output for timer 0. 2. interrupts can be selected to occur at one of five different times. (6) sio - sio0: 8 bit synchronous serial interface 1. lsb first/msb first function available 2. internal 8-bit baud-rate generator (maximum transmit clock period 4/3 t cyc ) 3. continuous automatic data communications (1 - 256 bits) - sio1: 8 bit asynchronous/synchronous serial interface mode 0: synchronous 8 bit serial io (2-wire or 3-wire, transmit clock 2 - 512 t cyc ) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 t cyc ) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 t cyc ) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) - sio2: 8 bit synchronous serial interface 1. lsb-first 2. built in 8-bit baud-rate generator (maximum clock period 4/3 t cyc ) 3. continuous automatic data communication (1 - 32 bytes) (7) ad converter - 8-bits 8-channels (8) pwm - 2 channel synchronous variable 12 bit pwm (9) parallel interface - rs, rd , wr , cs0 - cs2 outputs (reversible polarity) - read/write possible in 1 t cyc (10) remote control receiver circuit (connected to p73/int3/t0in terminal) - noise rejection function (noise rejection filter time constant can selected from 1/32/128 t cyc )
LC87F5164A 3/28 (11) watchdog timer - the watchdog timer period set by external rc. - watchdog timer can be set to produce interrupt, system reset (12) interrupts - 19-source, 10-vectored interrupts: 1. three level (low, high and highest) multiple interrupts are supported. during interrupt handling, an equal or lower level interrupt request is refused. 2. if interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence. in the case of equal priority levels, the vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1/sio2 9 00043h h or l adc 10 0004bh h or l port 0/t4/t5/pwm0, 1 priority level: x>h>l for equal priority levels, vector with lowest address takes precedence. (13) subroutine stack levels - 512 levels max. stack is located in ram (14) multiplication and divsion - 16 bit 8 bit (executed in 5 cycles) - 24 bit 16 bit (12 cycles) - 16 bit 8 bit ( 8 cycles) - 24 bit 16 bit (12 cycles) (15) oscillation circuits - on-chip rc oscillation circuit used for system clock - on-chip cf oscillation circuit used for system clock - on-chip crystal oscillation circuit used for system clock and time-base clock (16) standby function - halt mode halt mode is used to reduce power consumption. program execution is stopped. peripheral circuits still operate. 1. oscillation circuits are not stopped automatically 2. release on system reset - hold mode hold mode is used to reduce the power dissipation. both program execution and peripheral circuits are stopped. 1. cf, rc and crystal oscillation circuits stop automatically 2. release occurs on any of the following conditions input to the reset pin goes low a specified level is input to at least one of int0, int1, int2, int4, int5 an interrupt condition arises at port 0
LC87F5164A 4/28 - x?tal hold mode x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits except the base timer are stopped. 1. cf and rc oscillation circuits stop automatically 2. crystal oscillator is maintained in its state at hold mode inception. 3. release occurs on any of the following conditions input to the reset pin goes low a specified level is input to at least one of int0, int1, int2, int4, int5 an interrupt condition arises at port 0 an interrupt condition arises at the base-timer (17) factory shipment - delivery form qfp80e - delivery form sqfp80 (18) development tools - evaluation chip : lc876099 - emulator : eva87000 + ecb875100 (evaluation chip board) + pod875100 (pod)
LC87F5164A 5/28 pin assignment package dimension (unit : mm) 3174 sanyo : qip-80e 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pb4/d4 pb3/d3 pb2/d2 pb1/d1 pb0/d0 vss3 vdd3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pa0/cs2# lc87f5100a qip80 pb5/d5 pb6/d6 pb7/d7 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07 p06 p05 p04 p03 p02 p01 p00 vss2 vdd2 pwm0 pwm1 si2p3/sck20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pa1/cs1 # pa2/cs0 # pa3/wr # pa4/rd # pa5/rs p70/int0/t0lcp p71/int1/t0hcp p72/int2/t0i n p73/int3/t0i n res # xt1 xt2 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an 4 p85/an5 p86/an6 p87/an7 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 si2p2/sck2 si2p1/si2/sb2 si2p0/so2 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p34 p33 p32 p31 p30
LC87F5164A 6/28 pin assignment package dimension (unit : mm) 3220 sanyo : sqfp-80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pb6/d6 pb5/d5 pb4/d4 pb3/d3 pb2/d2 pb1/d1 pb0/d0 vss3 vdd3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a1 pc1/a1 pc0/a0 pa0/cs2# pa1/cs1# pa2/cs0# lc87f5100a sqfp80 pb7/d7 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in p07 p06 p05 p04 p03 p02 p01 p00 vss2 vdd2 pwm0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pa3/wr# pa4/rd # pa5/rs p70/int0/t0lcp p71/int1/t0hcp p72/int2/t0i n p73/int3/t0i n res# xt1 xt2 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/so2 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p34 p33 p32 p31 p30 p87/an7 p86/an6
LC87F5164A 7/28 qip name sqfp qip name sqfp 1 pa1/ cs1 79 41 si2p3/sck20 39 2 pa2/ cs0 80 42 pwm1 40 3 pa3/ wr 1 43 pwm0 41 4 pa4/ rd 2 44 vdd2 42 5 pa5/rs 3 45 vss2 43 6 p70/int0/t0lcp 4 46 p00 44 7 p71/int1/t0hcp 5 47 p01 45 8 p72/int2/t0in 6 48 p02 46 9 p73/int3/t0in 7 49 p03 47 10 res 8 50 p04 48 11 xt1 9 51 p05 49 12 xt2 10 52 p06 50 13 vss1 11 53 p07 51 14 cf1 12 54 p20/int4/t1in 52 15 cf2 13 55 p21/int4/t1in 53 16 vdd1 14 56 p22/int4/t1in 54 17 p80/an0 15 57 p23/int4/t1in 55 18 p81/an1 16 58 p24/int5/t1in 56 19 p82/an2 17 59 p25/int5/t1in 57 20 p83/an3 18 60 p26/int5/t1in 58 21 p84/an4 19 61 p27/int5/t1in 59 22 p85/an5 20 62 pb7/d7 60 23 p86/an6 21 63 pb6/d6 61 24 p87/an7 22 64 pb5/d5 62 25 p30 23 65 pb4/d4 63 26 p31 24 66 pb3/d3 64 27 p32 25 67 pb2/d2 65 28 p33 26 68 pb1/d1 66 29 p34 27 69 pb0/d0 67 30 p10/so0 28 70 vss3 68 31 p11/si0/sb0 29 71 vdd3 69 32 p12/sck0 30 72 pc7/a7 70 33 p13/so1 31 73 pc6/a6 71 34 p14/si1/sb1 32 74 pc5/a5 72 35 p15/sck1 33 75 pc4/a4 73 36 p16/t1pwml 34 76 pc3/a3 74 37 p17/t1pwmh/buz 35 77 pc2/a2 75 38 si2p0/so2 36 78 pc1/a1 76 39 si2p1/si2/sb2 37 79 pc0/a0 77 40 si2p2/sck2 38 80 pa0/ cs2 78
LC87F5164A 8/28 system block diagram cf rc x?tal clock generator interru p t control standb y control sio0 sio1 sio2 timer 0 timer 1 timer 4 timer 5 pwm 0 pwm 1 base timer bus interface port 0 port 1 port 3 port 7 port 8 adc int 0 - 3 noise re j ection filter port 2 int4,5 parallel interface port a port b port c acc b register alu psw rar ram stack pointer watch dog timer pc rom ir pla c register
LC87F5164A 9/28 pin assignment pin name i/o pin function option vss1 vss2 vss3 - negative power supply no vdd1 vdd2 vdd3 - positive power supply no port 0 p00 - p07 i/o 8-bit input/output port data direction can be specified in nibble units use of pull-up resistor can be specified in nibble units hold-release input input for port 0 interrupt yes port 1 p10 - p17 i/o 8-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions p10: sio0 data output p11: sio0 data input/bus input/output p12: sio0 clock input/output p13: sio1 data output p14: sio1 data input/bus input/output p15: sio1 clock input/output p16: timer 1 pwml output p17: timer 1 pwmh output/buzzer output yes port 2 8-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions p20-p23: int4 input/hold release input/timer 1 event input /timer 0l capture input/timer 0h capture input p24-p27: int5 input/hold release input/timer 1 event input /timer 0l capture input /timer 0h capture input interrupt receiver format rising falling rising/falling h level l level int4 int5 yes yes yes yes yes yes no no no no p20 - p27 i/o yes port 3 p30 - p34 i/o 5-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit yes (continued)
LC87F5164A 10/28 name i/o function description option port 7 4-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions p70: int0 input/hold release input/timer0l capture input /output for watchdog timer p71: int1 input/hold release input/timer0h capture input p72: int2 input/hold release input/timer 0 event input /timer0l capture input p73: int3 input(noise rejection filter attached input) /timer 0 event input/timer0h capture input interrupt receiver format rising falling rising/falling h level l level int0 int1 int2 int3 yes yes yes yes yes yes yes yes no no yes yes yes yes no no yes yes no no p70 - p73 i/o no port 8 p80 - p87 i/o 8-bit input/output port data direction can be specified for each bit other functions p80-p87: ad input port no port a pa0 - pa5 i/o 6-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions pa0: parallel interface output cs2 pa1: parallel interface output cs1 pa2: parallel interface output cs0 pa3: parallel interface output wr pa4: parallel interface output rd pa5: parallel interface output rs yes port b pb0 - pb7 i/o 8-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions pb0-pb7: parallel interface data input/output; address output yes port c pc0 - pc7 i/o 8-bit input/output port data direction can be specified for each bit use of pull-up resistor can be specified for each bit other functions pc0-pc7: parallel interface address output yes sio2 port si2p0 - si2p3 i/o 4-bit input/output port data direction can be specified for each bit other functions si2p0: sio2 data output si2p1: sio2 data output/bus input/output si2p2: sio2 clock input/output si2p3: sio2 clock output yes pwm0 o pwm0 output port no pwm1 o pwm1 output port no res i reset terminal no (continued)
LC87F5164A 11/28 name i/o function description option xt1 i input for 32.768khzcrystal oscillation other function input port when not in use, connect to vdd1. no xt2 i/o output for 32.768khzcrystal oscillation other function general purpose input port when not in use, set to oscillation mode and leave open circuit no cf1 i input terminal for ceramic oscillator no cf2 o output terminal for ceramic oscillator no
LC87F5164A 12/28 port output configuration output configuration and pull-up resistor options are shown in the following table. input is possible even when port is set to output mode. terminal option applies to: option output format pull-up resistor 1 cmos programmable (note 1) p00-p07 1 bit units 2 nch-open drain none 1 cmos programmable p10-p17 p20-p27 p30-p34 each bit 2 nch-open drain programmable 1 cmos programmable pa0-pa5 pb0-pb7(*) pc0-pc7 each bit 2 nch-open drain programmable p70 - none nch-open drain programmable p71-p73 - none cmos programmable p80-p87 - none nch-open drain none si2p0, si2p2 si2p3 pwm0, pwm1 - none cmos none si2p1 - none cmos (when used as standard port) nch-open drain (when used for sio2 data) none xt1 - none input only none xt2 - none output for 32.768khz crystal oscillation none note 1 programmable pull-up resisters of port 0 can be attatched in nibble units (p00-03, p04-07). (*) when in parallel interface mode, pb0-pb7 output format is cmos, regardless of any selected option. note: connect as follows to reduce noise on vdd and increase the back-up time. vss1, vss2 and vss3 must be connected together and grounded. example 1 : in hold mode, during backup, port output ?h? level is supplied from the back-up capacitor. example 2 : during backup in hold mode output is not held high and its value in unsettled. power supply back-up capacitor lsi vdd1 vdd2 vss1 vss2 vss3 vdd3 power supply back-up capacitor lsi vdd1 vdd2 vss1 vss2 vss3 vdd3
LC87F5164A 13/28 1. absolute maximum ratings at ta=25 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vddmax vdd1, vdd2, vdd3 vdd1=vdd2=vdd3 -0.3 +6.5 input voltage vi(1) xt1, xt2, cf1 -0.3 vdd+0.3 output voltage vo(1) pwm0, pwm1 -0.3 vdd+0.3 input/output voltage vio(1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c si2p00-si2p03 pwm0, pwm1 -0.3 vdd+0.3 v ioph(1) ports 0, 1, 2, 3 ports a, b, c si2p00-si2p03 pwm0, pwm1 cmos output for each pin. -10 peak output current ioph(2) p71-p73 for each pin. -5 ioah(1) p71-p73 the total of all pins. -5 ioah(2) port 1 pwm0, pwm1 port 3 si2p00-si2p03 the total of all pins. -30 ioah(3) ports 0, 2 the total of all pins. -20 ioah(4) port b the total of all pins. -20 high level output current total output current ioah(5) ports a, c the total of all pins. -20 iopl(1) p02-p07 ports 1, 2, 3 ports a, b, c si2p00-si2p03 pwm0, pwm1 for each pin. 20 iopl(2) p00, p01 for each pin. 30 peak output current iopl(3) ports 7, 8 for each pin. 15 ioal(1) port 7 the total of all pins. 5 ioal(2) port 8 the total of all pins. 5 ioal(3) port 1 pwm0, pwm1 port 3 si2p00-si2p03 the total of all pins. 50 ioal(4) ports 0, 2 the total of all pins. 70 ioal(5) port b the total of all pins. 40 low level output current total output current ioal(6) ports a, c the total of all pins. 40 ma maximun power dissipation pdmax qip80e sqfp80 ta=-20 to +70 c 350 mw operating temperature range topg -20 to 70 storage temperature range tstg -55 to 125 c
LC87F5164A 14/28 2. recommended operating range at ta=-20 c to +70 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit operating supply voltage range vdd(1) vdd1=vdd2 =vdd3 0.294 s tcyc 200 s 4.5 5.5 hold voltage vhd vdd1=vdd2 =vdd3 ram and the register data are kept in hold mode. 2.0 5.5 vih(1) ports 1, 2 si2p00 - 03 p71-p73 p70 port input /interrupt 4.5 - 5.5 0.3vdd +0.7 vdd vih(2) ports 0, 8 ports a, b, c 4.5 - 5.5 0.3vdd +0.7 vdd vih(3) port 70 watchdog timer input 4.5 - 5.5 0.9vdd vdd input high voltage vih(4) xt1, xt2, cf1, res 4.5 - 5.5 0.75vdd vdd vil(1) ports 1, 2 si2p00 - 03 p71-p73 p70 port input /interrupt 4.5 - 5.5 vss 0.1vdd +0.4 vil(2) ports 0, 8 ports a, b, c 4.5 - 5.5 vss 0.15vdd +0.4 vil(5) port 70 watchdog timer input 4.5 - 5.5 vss 0.8vdd -1.0 input low voltage vil(6) xt1, xt2, cf1, res 4.5 - 5.5 vss 0.25vdd v operation cycle time tcyc 4.5 - 5.5 0.294 200 s cf2 open circuit system clock divider set to 1/1 external clock duty=50 5% 4.5 - 5.5 0.1 10 external system clock frequency fexcf(1) cf1 cf2 open circuit system clock divider set to 1/2 4.5 - 5.5 0.2 20.4 mhz (note 1) the oscillation constant is shown in tables 1 and 2.
LC87F5164A 15/28 3. electrical characteristics at ta=-20 c to +70 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c si2p00-si2p03 res pwm0, pwm1 output disable pull-up resistor off vin=vdd (including off state leak current of output tr.) 4.5 - 5.5 1 iih(2) xt1, xt2 when specified as an input port. vin=vdd 4.5 - 5.5 1 input high current iih(3) cf1 vin=vdd 4.5 - 5.5 15 iil(1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c si2p00-si2p03 res pwm0, pwm1 output disable pull-up resistor off vin=vss (including off state leak current of output tr.) 4.5 - 5.5 -1 iil(2) xt1, xt2 when specified as an input port vin=vss 4.5 - 5.5 -1 input low current iil(3) cf1 vin=vss 4.5 - 5.5 -15 a voh(1) ports 0, 1, 2, 3 ports b, c ioh=-1.0ma 4.5 - 5.5 vdd-1 voh(2) si2p00-si2p03 pwm0, pwm1 ioh=-0.1ma 4.5 - 5.5 vdd-0.5 voh(3) ioh=-5.0ma 4.5 - 5.5 vdd-1 voh(4) port a ioh=-0.4ma 4.5 - 5.5 vdd-0.5 output high current voh(5) port 7 ioh=-0.4ma 4.5 - 5.5 vdd-1 v (continued)
LC87F5164A 16/28 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vol(1) ports 0, 1, 2, 3 ports b, c iol=10ma 4.5 - 5.5 1.5 vol(2) vol(3) si2p00-si2p03 pwm0, pwm1 iol=1.6ma 4.5 - 5.5 0.4 vol(4) p00, p01 iol=30ma 4.5 - 5.5 1.5 vol(5) vol(6) ports 7, 8 iol=1ma 4.5 - 5.5 0.4 vol(7) iol=15ma 4.5 - 5.5 1.5 output low current vol(8) port a iol=2ma 4.5 - 5.5 0.4 v pull-up resistor rpu ports 0, 1, 2, 3 port 7 ports a, b, c voh=0.9vdd 4.5 - 5.5 15 40 70 k ? hysteresis voltage vhis res 4.5 - 5.5 0.1vdd v pin capacitance cp all pins every other terminal connected to vss. f=1mhz ta=25 c 4.5 - 5.5 10 pf
LC87F5164A 17/28 4. serial input/output characteristics at ta=-20 c to +70 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle tsck(1) 2 tsckl(1) 1 low level pulse width tsckla(1) 1 tsckh(1) 1 high level pulse width tsckha(1) sck0(p12), si2p2 refer to figure 6 4.5 - 5.5 3(sio0) 5(sio2) cycle tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1(p15) refer to figure 6 4.5 - 5.5 1 cycle tsck(3) 4/3 tcyc tsckl(3) cmos output option refer to figure 6 1/2 sck0(p12) sio0 3/4 low level pulse width tsckla(2) si2p2, si2p3 sio2 1 tsckh(3) 1/2 sck0(p12) sio0 2 high level pulse width tsckha(2) sck0(p12), si2p2 si2p3 si2p2, si2p3 sio2 4.5 - 5.5 7/4 tsck cycle tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) cmos output option refer to figure 6 4.5 - 5.5 1/2 tsck data set-up time tsdi 0.03 serial input data hold time thdi sb0(p11), sb1(p14), si2p1 si0 si1 data set-up to si0clk refer to figure 6 4.5 - 5.5 0.03 serial output output delay time tdd0 so0(p10), so1(p13), sb0(o11), sb1(p14), si2p0, si2p1 data set-up to si0clk when port is open drain: time delay from si0clk trailing edge to the so data change. refer to figure 6 4.5 - 5.5 1/3tcyc +0.05 s
LC87F5164A 18/28 5. parallel input/ output characteristics at ta=-20 c to +70 c, vss1=vss2=vss3=0v note: port a terminals used as rs, wr , rd and cs should be set to cmos format. please refer to figures 8 and 9 for parallel output timing waveforms. ratings parameter symbol pins conditions vdd[v] min. typ. max. unit write cycle, read cycle tc(1) 4.5 - 5.5 1 tcyc tsa(1) wr (pa3), pb0-pb7 rd (pa4), pc0-pc7 4.5 - 5.5 1/3tcyc -30ns address set-up time tsa(2) rd (pa4), pc0-pc7 from address set-up until control signal changes 4.5 - 5.5 2/3tcyc -30ns tha(1) rd (pa4), pc0-pc7 from change of rd until address change 4.5 - 5.5 1/6tcyc tcyc & ns address hold time tha(2) wr (pa3), pc0-pc7 from change of wr until address change 4.5 - 5.5 5 ns tsrs(1) wr (pa3), rs(pa5), cs (pax) from change of rs, cs until change in wr 4.5 - 5.5 1/6tcyc -15ns tsrs(2) rd (pa4), rs(pa5) 4.5 - 5.5 1/6tcyc -15ns rs set-up tie tsrs(3) rd (pa4), rs(pa5) from change of rs until change in rd 4.5 - 5.5 1/3tcyc -15ns tscs(1) rd (p a 4 ) , c s (pax) from change in cs until change in rd 4.5 - 5.5 1/3tcyc -15ns cs set-up time tscs(2) wr (p a 3 ) , cs (pax) from change in cs until change in wr 4.5 - 5.5 2/3tcyc -15ns tcyc & ns thrs(1) wr (pa3), rs(pa5) from change in wr until change in rs 4.5 - 5.5 0 ns thrs(2) rd (pa4), rs(pa5), cs (pax) 4.5 - 5.5 1/6tcyc tcyc & ns rs hold time thrs(3) rd (pa4), rs(pa5), cs (pax) from change in rd until change in rs, cs 4.5 - 5.5 0 ns thcs(1) rd (pa4), rs(pa5) from change in rd until change in cs 4.5 - 5.5 1/6tcyc tcyc & ns cs hold time thcs(2) wr (pa3), rs(pa5) from change in wr until change in cs 4.5 - 5.5 0 ns twrh(1) wr (pa3) 4.5 - 5.5 1/6tcyc -5ns 1/6 tcyc wr ?h? pulse width twrh(2) wr (pa3) 4.5 - 5.5 2/3tcyc -5ns 2/3 tcyc twrl(1) wr (pa3) 4.5 - 5.5 1/6tcyc -5ns 1/6 tcyc wr ?l? pulse width twrl(2) wr (pa3) 4.5 - 5.5 1/3tcyc -5ns 1/3 tcyc tcyc & ns (continued)
LC87F5164A 19/28 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit trdh(1) rd (pa4) 4.5 - 5.5 1/6tcyc -5ns 1/6 tcyc rd ?h? pulse width trdh(2) rd (pa4) 4.5 - 5.5 1/3tcyc -5ns 1/3 tcyc trdl(1) rd (pa4) 4.5 - 5.5 1/3tcyc -5ns 1/3 tcyc rd ?l? pulse width trdl(2) rd (pa4) 4.5 - 5.5 1/2tcyc -5ns 1/2 tcyc tddt(1) rd (pa4), pb0-pb7 4.5 - 5.5 1/6tcyc -15ns data write permission delay tddt(2) rd (pa4), pb0-pb7 time for permission, from rd leading edge until input data set-up (note 1) 4.5 - 5.5 1/3tcyc -15ns tcyc & ns input data set-up time tsdtr(1) rd (pa4), pb0-pb7 from input data set- up to rd leading edge. (note 2) 4.5 - 5.5 40 ns input data hold time thdtr(1) rd (pa4), pb0-pb7 from rd leading edge until input data hold 4.5 - 5.5 0 ns output data set-up time tsdtw(1) rd (pa4), pb0-pb7 4.5 - 5.5 1/3tcyc -30ns output data set-up time tsdtw(2) rd (pa4), pb0-pb7 from output data set- up until wr leading edge 4.5 - 5.5 1/3tcyc -30ns tcyc & ns thdtw(1) 4.5 - 5.5 0 output data hold time thdtw(2) rd (pa4), pb0-pb7 from wr leading edge until output data hold 4.5 - 5.5 0 ns note 1 : time until incorrect data of low is disappeared. note 2 : incorrect data of low is not output in the period between trdl(1) - tddt(1). 6. pulse input conditions at ta=-20 c to +70 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p20-p23) int5(p24-p27) interrupt acceptable events to timer 0 and 1 can be input. 4.5 - 5.5 1 tpih(2) tpil(2) int3(p73) (the noise rejection clock select to 1/1.) interrupt acceptable events to timer 0 can be input. 4.5 - 5.5 2 tpih(3) tpil(3) int3(p73) (the noise rejection clock select to 1/32.) interrupt acceptable events to timer 0 can be input. 4.5 - 5.5 64 tpih(4) tpil(4) int3(p73) (the noise rejection clock select to 1/128.) interrupt acceptable events to timer 0 can be input. 4.5 - 5.5 256 t cyc high/low level pulse width tpil(5) res reset acceptable 4.5 - 5.5 200 s
LC87F5164A 20/28 7. ad converter characteristics at ta=-20 c to +70 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5 - 5.5 8 bit absolute precision et (note 2) 4.5 - 5.5 1.5 lsb ad conversion time =32 tcyc (adcr2=0) (note 3) 4.5 - 5.5 15.10 (tcyc= 0.588 s) 97.92 (tcyc= 3.06 s) conversion time tcad ad conversion time =64 tcyc (adcr2=1) (note 3) 4.5 - 5.5 15.10 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 4.5 - 5.5 vss vdd v iainh vain=vdd 4.5 - 5.5 1 analog port input current iainl an0(p80) - an7(p87) vain=vss 4.5 - 5.5 -1 a (note 2) absolute precision not including quantizing error (1/2 lsb). (note 3) conversion time means time from executing ad conversion instruction to loading complete digital value to register.
LC87F5164A 21/28 8. current dissipation characteristics at ta=-20 c to +70 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=10mhz for ceramic resonator oscillation fmx?tal=32.768khz for crystal oscillation system clock: cf oscillation internal rc oscillation stopped. divider: 1/1 4.5 - 5.5 18 35 current flow during basic operation (note 4) iddop(2) vdd1 =vdd2 =vdd3 cf1=20mhz for external clock fmx?tal=32.768khz for crystal oscillation system clock : cf1 internal rc oscillation stopped. divider 1/2 4.5 - 5.5 18 35 ma iddhalt(1) halt mode fmcf=10mhz for ceramic resonator oscillation fmx?tal=32.768khz for crystal oscillation system clock: cf oscillation internal rc oscillation stopped. divider 1/1 4.5 - 5.5 6 12 current flow: halt mode (note 4) iddhalt(2) vdd1 =vdd2 =vdd3 cf1=20mhz external clock fmx?tal=32.768khz for crystal oscillation system clock : cf1 internal rc oscillation stopped. divider 1/2 4.5 - 5.5 7 14 ma current flow: hold mode (note 4) iddhold(1 ) vdd1 hold mode cf1=vdd or open circuit (when using external clock) 4.5 - 5.5 0.01 25 a current flow: date/time clock hold mode iddhold(2 ) vdd1 date/time clock hold mode cf1=vdd or open circuit (when using external clock) fmx?tal=32.768khz for crystal oscillation 4.5 - 5.5 35 100 a (note 4) the currents of output transistors and pull-up mos transistors are ignored.
LC87F5164A 22/28 9. f-rom write characteristics at ta=+10 c to +55 c, vss1=vss2=vss3=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit on-board write current iddfw(1) vdd1 128-byte write including erase current 4.5 - 5.5 30 65 ma write time tfw(1) 128-byte write including data erase excluding time to fetch 128 byte data 4.5 - 5.5 4.2 7.0 ms
LC87F5164A 23/28 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max notes csa10.0mtz 33pf 33pf 0 ? 4.5 to 6.0v 0.05ms 0.50ms murata cst10.0mtw (30pf) (30pf) 0 ? 4.5 to 6.0v 0.05ms 0.50ms built in c1,c2 10mhz kyocera kbr-10.0m 33pf 33pf 0 ? 4.5 to 6.0v 0.05ms 0.50ms csa4.00mg 33pf 33pf 0 ? 4.5 to 6.0v 0.05ms 0.50ms murata cst4.00mgw (30pf) (30pf) 0 ? 4.5 to 6.0v 0.05ms 0.50ms built in c1,c2 4mhz kyocera kbr-4.0msa 33pf 33pf 0 ? 4.5 to 6.0v 0.05ms 0.50ms *the oscillation stabilizing time is a period until the oscillation becomes stable after vdd becomes higher than minimum operating voltage. (refer to figure4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 2. subsystem clock oscillation circuit characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 c4 rf rd2 operating supply voltage range typ max notes 32.768khz seiko epson c-002rx 12pf 15pf open 300k ? 4.5 to 6.0v *the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode. (refer to figure4) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point cf1 cf2 cf c1 c2 xt1 xt2 rf c3 c4 x?tal rd2 rd1 0.5vdd
LC87F5164A 24/28 reset time and oscillation stable time hold release signal and oscillation stable time figure 4 oscillation stabilizing time power suppl y res# internal rc resonator oscillation cf1 , cf2 xt1 , xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution mode vdd vdd limit gnd internal rc resonator oscillation cf1, cf2 xt1, xt2 operation mode hold release il without hold release hold release signal valid tmscf tmsxtal hold halt
LC87F5164A 25/28 (note) set cres, rres values such that reset time exceeds 200 s. figure 5 reset circuit figure 6 serial input/output test condition figure 7 pulse input timing condition c res vdd r res res data ram transmission period (only sio0,2) di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 si0clk: datain: dataout: dataout: datain: si0clk: dataout: datain: si0clk: tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transmission period (only sio0,2) tpil tpih
LC87F5164A 26/28 parallel input/output timing waveform : indirect setting, read mode note: port a terminals used as rs, wr , rd and cs should be set to cmos format. parallel input/output timing waveform : indirect setting, write mode note: port a terminals used as rs, wr , rd and cs should be set to cmos format. figure 8 indirect mode: parallel timing waveforms tsrs ( 1 ) adr/data: cs#: rs: wr#: rd#: datain: tc ( 1 ) read cycle tsa ( 1 ) addr thrs ( 1 ) twrh ( 1 ) twrl ( 1 ) tsrs ( 2 ) trdl ( 1 ) thrs ( 2 ) trdh ( 1 ) tsdtr ( 1 ) tddt ( 1 ) thdtr ( 1 ) data h adr/data: cs#: rs: wr#: rd#: datain: tc ( 1 ) write cycle data addr tsa ( 1 ) tsrs ( 1 ) thrs ( 1 ) thdtw ( 1 ) thrs ( 3 ) tsrs ( 3 ) tsdtw ( 1 ) twrh ( 1 ) twrl ( 1 ) twrl ( 2 )
LC87F5164A 27/28 parallel input/output timing waveform : direct setting, read mode note: port a terminals used as rs, wr , rd and cs should be set to cmos format. parallel input/output timing waveform : direct setting, write mode note: port a terminals used as rs, wr , rd and cs should be set to cmos format. figure 9 direct mode: parallel input/output timing diagrams data h tc ( 1 ) addr tsa ( 1 ) tscs ( 1 ) trdh ( 2 ) trdl ( 2 ) tddt ( 2 ) tsdtr ( 1 ) thdtr ( 1 ) tha ( 1 ) thcs ( 1 ) adr: cs#: data: wr#: rd#: datain: tc ( 1 ) addr tsa ( 2 ) tscs ( 2 ) twrl ( 2 ) tsdtw ( 2 ) thdtw ( 2 ) tha ( 2 ) thcs ( 2 ) adr: cs#: data: wr#: rd#: datain: data twrh ( 2 ) read cycle write cycle
LC87F5164A 28/28 ps

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